/* In master mode, control CS by user instead of AF. */ gpio_mode_setup(GPIO_SPI_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_SPI_CS_PIN); gpio_set_output_options(GPIO_SPI_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_SPI_CS_PIN);
spi_disable(SPI1); spi_reset(SPI1);
/* Set up in master mode. */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_64, /* Clock baudrate. */ SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, /* CPOL = 0. */ SPI_CR1_CPHA_CLK_TRANSITION_2, /* CPHA = 1. */ SPI_CR1_DFF_8BIT, /* Data frame format. */ SPI_CR1_MSBFIRST); /* Data frame bit order. */ spi_set_full_duplex_mode(SPI1);
/* * CS pin is not used on master side at standard multi-slave config. * It has to be managed internally (SSM=1, SSI=1) * to prevent any MODF error. */ spi_enable_software_slave_management(SPI1); /* SSM = 1. */ spi_set_nss_high(SPI1); /* SSI = 1. */
spi_deselect(); spi_enable(SPI1); }
staticvoidspi_rq_setup(void) { /* Set RQ pin to input floating. */ gpio_mode_setup(GPIO_SPI_RQ_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_SPI_RQ_PIN);
/** * @brief USART2 Interrupt service routine. */ voidusart2_isr(void) { uint8_t indata = usart_recv(USART2); /* Read received data. */
spi_select(); spi_send(SPI1, indata);
/* Wait for SPI transmit complete. */ while (!(SPI_SR(SPI1) & SPI_SR_TXE)) /* Wait for 'Transmit buffer empty' flag to set. */ { } while ((SPI_SR(SPI1) & SPI_SR_BSY)) /* Wait for 'Busy' flag to reset. */ { }
spi_deselect();
/* Clear 'Read data register not empty' flag. */ USART_SR(USART2) &= ~USART_SR_RXNE; }
spi_select(); spi_send(SPI1, 0x00); /* Just for beget clock signal. */ while ((SPI_SR(SPI1) & SPI_SR_BSY)) /* Wait for 'Busy' flag to reset. */ { } uint8_t indata = spi_read(SPI1);
while ((SPI_SR(SPI1) & SPI_SR_BSY)) /* Wait for 'Busy' flag to reset. */ { } spi_deselect();
/* In master mode, control CS by user instead of AF. */ gpio_mode_setup(GPIO_SPI_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_SPI_CS_PIN); gpio_set_output_options(GPIO_SPI_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_SPI_CS_PIN);
spi_disable(SPI1); spi_reset(SPI1);
/* Set up in master mode. */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_64, /* Clock baudrate. */ SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, /* CPOL = 0. */ SPI_CR1_CPHA_CLK_TRANSITION_2, /* CPHA = 1. */ SPI_CR1_DFF_8BIT, /* Data frame format. */ SPI_CR1_MSBFIRST); /* Data frame bit order. */ spi_set_full_duplex_mode(SPI1);
/* * CS pin is not used on master side at standard multi-slave config. * It has to be managed internally (SSM=1, SSI=1) * to prevent any MODF error. */ spi_enable_software_slave_management(SPI1); /* SSM = 1. */ spi_set_nss_high(SPI1); /* SSI = 1. */
NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to prevent any MODF error. 參考自 RM0390 Rev6 P.852。
/** * @brief USART2 Interrupt service routine. */ voidusart2_isr(void) { uint8_t indata = usart_recv(USART2); /* Read received data. */
spi_select(); spi_send(SPI1, indata);
/* Wait for SPI transmit complete. */ while (!(SPI_SR(SPI1) & SPI_SR_TXE)) /* Wait for 'Transmit buffer empty' flag to set. */ { } while ((SPI_SR(SPI1) & SPI_SR_BSY)) /* Wait for 'Busy' flag to reset. */ { }
spi_deselect();
/* Clear 'Read data register not empty' flag. */ USART_SR(USART2) &= ~USART_SR_RXNE; }
spi_select(); spi_send(SPI1, 0x00); /* Just for beget clock signal. */ while ((SPI_SR(SPI1) & SPI_SR_BSY)) /* Wait for 'Busy' flag to reset. */ { } uint8_t indata = spi_read(SPI1);
while ((SPI_SR(SPI1) & SPI_SR_BSY)) /* Wait for 'Busy' flag to reset. */ { } spi_deselect();